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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
Signal Functional Description (Sheet 3 of 7)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
Description  
I/O  
Type  
Notes  
MII: Transmit data enabled  
RMII 0: Transmit data enabled  
EMCTxEn,  
EMC0TxEn  
5V tolerant  
3.3V LVTTL  
O
EMCTxErr,  
EMC1TxEn  
MII: Transmit error:  
RMII: Transmit data enabled  
5V tolerant  
3.3V LVTTL  
O
External Slave Peripheral Interface  
Used by the PPC440GP to indicate that data transfers have  
5V tolerant  
DMAAck0:3  
DMAReq0:3  
EOT0:3/TC0:3  
O
I
occurred.  
3.3V LVTTL  
Used by slave peripherals to indicate they are prepared to transfer  
data.  
5V tolerant  
3.3V LVTTL  
1, 5  
1, 5  
5V tolerant  
3.3V LVTTL  
End Of Transfer/Terminal Count.  
I/O  
Peripheral address bus used by PPC440GP when not in external  
master mode, otherwise used by external master.  
Note: PerAddr00 is the most significant bit (msb) on this bus.  
5V tolerant  
3.3V LVTTL  
PerAddr00:31  
I/O  
1
5V tolerant  
PerWBE0:3  
PerBLast  
External peripheral data bus byte enables.  
I/O  
I/O  
O
1, 2  
1, 4  
2
3.3V LVTTL  
Used by either the peripheral controller, DMA controller, or  
external master to indicates the last transfer of a memory access.  
5V tolerant  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
PerCS0:7  
External peripheral device select.  
Peripheral data bus used by PPC440GP when not in external  
master mode, otherwise used by external master.  
Note: PerData00 is the most significant bit (msb) on this bus.  
5V tolerant  
PerData00:31  
PerOE  
I/O  
O
1
3.3V LVTTL  
Used by either peripheral controller or DMA controller depending  
upon the type of transfer involved. When the PPC440GP is the  
bus master, it enables the selected device to drive the bus.  
5V tolerant  
3.3V LVTTL  
2
1
5V tolerant  
3.3V LVTTL  
PerPar0:3  
PerReady  
External peripheral data bus byte parity.  
I/O  
I
5V tolerant  
3.3V LVTTL  
Used by a peripheral slave to indicate it is ready to transfer data.  
Used by the PPC440GP when not in external master mode, as  
output by either the peripheral controller or DMA controller  
depending upon the type of transfer involved. High indicates a  
read from memory, low indicates a write to memory.  
Otherwise, it used by the external master as an input to indicate  
the direction of transfer.  
5V tolerant  
PerR/W  
PerWE  
I/O  
O
1, 2  
2
3.3V LVTTL  
Write Enable. Low when any of the four PerWBE0:3 signals are  
low.  
5V tolerant  
3.3V LVTTL  
50  
AMCC  
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