Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 22. Input Capacitance
Parameter
Symbol
Maximum
2.9
Unit
pF
Notes
CIN1
2.5V/1.8V DDR
3.3V LVTTL
PCI
CIN2
CIN3
CIN5
CIN6
2.1
pF
2.5
pF
3.3V tolerant CMOS
USB
2.4
pF
3.0
pF
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance with operating
conditions shown in Table 10 on page 66. AC specifications are characterized with
50pF
V
= +1.5V, T = +85 °C and a 50pF test load as shown in the figure to the right.
DD
C
DDR2/1 SDRAM I/O Specifications
The DDR2/1 SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut
from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However, MemClkOut is
the same frequency as the PLB clock signal and is in phase with the PLB clock signal. The phase skew between
MemClkOut and the PLB clock is affected by the loading on MemClkOut.
Read capture logic in the DDR controller captures read data using a delayed version of DQS and internally re-
synchronizes the data to the PLB clock.The PPC440EPx contains three independently programmable digital delay
lines (DLLs) that control the timing of the indicated signals in read and write operations:
1. DQS (with respect to MemClkOut) for write operations.
2. MemData, ECC, and DM (with respect to MemClkOut) for write operations.
3. DQS (with respect to inbound MemData) for read operations.
There is also a master delay line for calibration. Programming details can be found in the PPC440EPx Embedded
Processor Users Manual.
The signals are terminated as indicated in Figure 9 for the DDR timing data in the following sections.
The PPC440EPx uses a clock forwarding scheme in which it drives the clock to the memory devices.
Data signals are divided into eight subgroups—one for each byte lane (see Table 27 on page 89)— plus a ninth
subgroup for the ECC byte lane. These signals include MemData00:63, DQS0:8, DM0:8, and ECC0:7 signals.
Signals within a data subgroup (byte lane) should be routed together.
Command Bus Operation
The command bus (MemAddr, RAS, CAS, WE, BA, ClkEn, BankSel, MemODT) is driven 180° out-of-phase with
MemClkOut, and has no corresponding delay line. Therefore, board designers must consider two different types of
systems: 1) registered DIMMs and 2) unbuffered DIMMs. The system clocking design must also be considered. To
avoid crosstalk, the command bus signals and the data signals should not be routed together.
84
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