Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is
generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated
over best case and worst case processes with speed, junction temperature, and voltage as follows:
Table 24. DDR SDRAM Write Operation Conditions
Case
Best
Process Speed
Fast
Junction Temperature (°C)
Voltage (V)
+1.6
−40
Worst
Slow
+125
+1.425
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 9.
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 10. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut
T
SA
Addr/Cmd
T
T
SK
DS
T
HA
T
DS
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
T
= Delay from falling edge of MemClkOut to rising/falling edge of signal (skew)
= Setup time for address and command
SK
SA
T
= Hold time for address and command signals from MemClkOut
HA
SD
HD
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
T
DS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
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