Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 21. I/O Specifications—EBC, EBMI, DMA and NAND Flash Interfaces
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
External Slave Peripheral Interface
DMAAck0:3
6
1
19.1
n/a
8.7
n/a
8.7
8.7
8.7
8.7
8.7
6.6
8.7
8.7
8.7
8.7
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
DMAReq0:3
EOT0:3/TC0:3
PerAddr02:31
PerBLast
4
4
4
4
1
1
1
1
6
6
6
6
6
6
6
1
1
1
1
1
1
1
19.1
19.1
19.1
19.1
19.1
14.6
19.1
19.1
19.1
19.1
PerCS0:5
PerData00:15
PerData16:31
PerOE
4
4
1
1
PerReady
4
4
4
1
1
1
PerR/W
6
6
1
1
PerWBE0:1
External Master Peripheral Interface
BusReq
ExtAck
6
6
1
1
19.1
19.1
19.1
19.1
19.1
n/a
8.7
8.7
8.7
8.7
8.7
n/a
n/a
8.7
n/a
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
ExtReq
4
1
ExtReset
HoldAck
HoldReq
HoldPri
6
6
1
1
4
4
1
1
n/a
PerClk
19.1
n/a
1
PerErr
4
1
NAND Flash Interface
NFALE
6
6
6
1
1
1
19.1
19.1
19.1
n/a
8.7
8.7
8.7
n/a
8.7
8.7
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
NFCE0:3
NFCLE
NFRdyBusy
NFREn
4
1
6
6
1
1
19.1
19.1
NFWEn
AppliedMicro Proprietary
83
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
