Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 20. I/O Specifications—PCI, USB, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. SMIISync is a weak driver. Redrive SMIISync when driving more than one load.
3. TDO timing is referenced to the falling edge of TCK.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
PCI Interface
PCIAD31:00
PCIC3:0/BE3:0
PCIDevSel
PCIFrame
PCIGnt0:5
PCIIDSel
3
3
5
5
0
0
0
0
6
6
6
6
6
2
2
2
2
2
0.5
0.5
0.5
0.5
0.5
n/a
0.5
0.5
0.5
0.5
n/a
n/a
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
n/a
1.5
1.5
1.5
1.5
n/a
n/a
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
5
0
PCIINT
async
async
PCIIRDY
5
5
5
5
0
0
0
0
6
6
6
2
2
2
PCIClk
PCIClk
PCIClk
PCIClk
PCIPar
PCIPErr
PCIReq0:5
PCIReset
PCISErr
5
5
5
0
0
0
6
6
6
2
2
2
PCIClk
PCIClk
PCIClk
PCIStop
PCITRDY
Ethernet MII Interface
GMCCD
5.1
5.1
5.1
5.1
n/a
5.1
5.1
5.1
5.1
n/a
5.1
5.1
6.8
6.8
6.8
6.8
n/a
6.8
6.8
6.8
6.8
n/a
6.8
6.8
async
async
GMCCrS
GMCMDClk
GMCMDIO
GMCRxClk
GMCRxD0:3
GMCTxD0:3
GMCRxDV
GMCRxEr
GMCTxClk
GMCTxEr
GMCMDClk
1
10
10
GMCRxClk
GMCTxClk
GMCRxClk
GMCRxClk
10
1
10
10
10
10
10
10
1
1
GMCTxClk
GMCTxClk
GMCTxEn
Ethernet GMII Interface
GMCCD
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
async
async
GMCCrS
GMCGTxClk
GMCMDClk
GMCMDIO
GMCRxClk
GMCRxD0:3
GMCTxD0:3
GMCRxDV
GMCRxEr
GMCTxEr
GMCMDClk
1
2
0
GMCRxClk
GMCGTxClk
GMCRxClk
GMCRxClk
GMCGTxClk
GMCGTxClk
2.5
1
2
2
0
0
2.5
2.5
1
1
GMCTxEn
80
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