Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Termination Model
Figure 9. DDR SDRAM Simulation Signal Termination Model
MemClkOut
10pF
10pF
120Ω
MemClkOut
V
= SOV /2
DD
TT
PPC440EPx
50
Ω
Addr/Ctrl (DDR2)
Addr/Ctrl/Data/DQS/DM (DDR1)
30pF
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
Table 23. DDR SDRAM Output Driver Specifications
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (maximum)
Write Data
MemData00:63
ECC0:7
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
DM0:8
MemClkOut
MemAddr00:13
BA0:2
RAS
CAS
WE
BankSel0:1
ClkEn
DQS0:8
MemODT0:1
86
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