Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 25. I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 166MHz.
TDS (ns)
Signal Name
Minimum
−0.030
−0.030
−0.050
−0.110
−0.140
−0.120
−0.060
−0.010
−0.140
Maximum
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
+0.650
+0.620
+0.580
+0.480
+0.410
+0.480
+0.580
+0.690
+0.420
Table 26. I/O Timing—DDR SDRAM T , T , and T
SK SA
HA
Notes:
1. Clock speed is 166MHz. TSK is referenced to MemClkOut falling edge. TSA and THA are referenced to MemClkOut rising
edge.
2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs,
use the following values by subtracting them from T and adding them to T and T :
SA
SK
HA
5 loads adjust by 0.41ns
9 loads adjust by 1.12ns
18 loads adjust by 2.12ns
3. To obtain adjusted TSA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract
TSK maximum (0.5TCYC − TSKmax).
4. To obtain adjusted THA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add
TSK minimum (0.5TCYC + TSKmin).
TSK (ns)
TSA (ns)
THA (ns)
Signal Name
Minimum
Maximum
Minimum
Minimum
MemAddr00:13
BA0:2
BankSel0:1
ClkEn
-0.960
-0.270
3.27
2.04
CAS
RAS
WE
88
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