Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Figure 8. Setup and Hold Timing Waveforms for RGMII Signals
GMCnTxClk
TskewT
GMCnTxD/Ctl
Valid
Valid
GMCnRxClk
TskewR
GMCnRxD/Ctl
Valid
Valid
Table 19. RGMII I/O Timing
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
TskewR
(min)
TskewR
(max)
TskewT
(min)
TskewT
(max)
I/O H
(min)
I/O L
(min)
GMCnRxClk
GMCnRxD0:3
GMCnRxCtl
GMCnTxClk
GMCnTxD0:3
GMCnTxCtl
Notes:
–
–
–
–
n/a
n/a
n/a
5.1
5.1
5.1
n/a
n/a
n/a
6.8
6.8
6.8
–
1.0
1.0
v
2.8
2.8
–
n/a
n/a
–
n/a
n/a
–
GMCnRxClk
GMCnRxClk
–
1
1
n/a
n/a
n/a
n/a
-0.5
-0.5
0.5
0.5
GMCnTxClk
GMCnTxClk
1. Assumes GMCnRxClk is delayed either on the board or by the PHY to ensure adequate timing margin.
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