Chapter 16: Understanding Timing in MAX II Devices
16–5
Calculating Timing Delays
Calculating Timing Delays
You can calculate approximate pin-to-pin timing delays for MAX II devices with the
timing model shown in Figure 16–1 and by referring to the DC and Switching
Characteristics chapter in the MAX II Device Handbook. Each external timing parameter
is calculated from a combination of internal timing parameters. Figure 16–2 through
Figure 16–6 show the external timing parameters for the MAX II device family. To
calculate the delay for a signal that follows a different path through the MAX II
device, refer to the timing model to determine which internal timing parameters to
add together.
For the most precise timing results, use the Quartus II Timing Analyzer, which
accounts for the effects of secondary factors such as placement and fan-out.
Figure 16–2. External Timing Parameter (tPD1
)
Note (1)
TRI
MAX II
Device
LUT
Note to Figure 16–2:
(1) tPD1 = tIN + N x tR4/4 + M x tC4/4 + tLUT + tCOMB + tFASTIO + (tOD + ΔtOD
)
Table 16–4 lists the numbers of LABs according to device density.
Table 16–4. Numbers of LABs According to Device Density
Device Density
EPM240
N LAB Rows
M LAB Columns
4
7
6
EPM570
12
16
20
EPM1270
EPM2210
10
13
DtOD is the adder delay (see note to Figure 16–2) for the tOD microparameter when
using an I/O standard other than 3.3-V LVTTL with 16 mA current strength.
f
Refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook for
adder delay values.
The following is an example:
tPD1 for the EPM240 device using an I/O standard of 3.3-V LVTTL fast slew rate with a
drive strength of 16 mA:
tPD1 = tIN + 4 × tR4/4 + 6 x tC4/4 + tLUT + tCOMB + tFASTIO + tOD……(a)
tPD1 for the EPM240 device using an I/O standard of 2.5-V LVTTL fast slew rate with a
drive strength of 7 mA: tPD1 = (a) + (DtOD of 2.5-V LVTTL fast slew 7 mA)
© October 2008 Altera Corporation
MAX II Device Handbook
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