16–8
Chapter 16: Understanding Timing in MAX II Devices
Conclusion
■
■
Distance between the signal source and destination
Various interconnect lengths where some interconnects are truncated at the edge
of the device
Conclusion
The MAX II device architecture has predictable internal timing delays that can be
estimated based on signal synthesis and placement. The Quartus II Timing Analyzer
provides the most accurate timing information. However, you can use the timing
model along with the timing parameters listed in the DC and Switching Characteristics
chapter in the MAX II Device Handbook to estimate a design’s performance before
compilation. Both methods enable you to accurately predict your design’s in-system
timing performance.
Referenced Documents
This chapter references the following document:
■
DC and Switching Characteristics chapter in the MAX II Device Handbook
Document Revision History
Table 16–5 shows the revision history for this chapter.
Table 16–5. Document Revision History
Date and Revision
Changes Made
Summary of Changes
October 2008,
version 2.1
■ Updated New Document Format.
—
December 2007,
version 2.0
■ Updated tPD2 information in Table 16–1.
■ Added tCOMB information in Table 16–2.
■ Updated Figure 16–1.
—
■ Updated Note (1) to Figure 16–2.
■ Updated “Calculating Timing Delays” section.
■ Added “Referenced Documents” section.
■ Added document revision history.
December 2006,
version 1.4
—
—
—
—
January 2005,
version 1.3
■ Previously published as Chapter 17. No changes to content.
■ Added section Programmable Input Delay.
December 2004,
version 1.2
June 2004,
version 1.1
■ Updated Table 16–1. Various parameter naming updates.
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
