16–4
Chapter 16: Understanding Timing in MAX II Devices
Timing Models
Table 16–3. Internal Timing Microparameters for MAX II UFM (Part 2 of 2)
Parameter
tEB
Description
Maximum delay between ERASErising edge to UFM BUSYsignal rising edge.
Minimum delay allowed from UFM BUSYsignal going low to ERASEsignal going low.
Maximum length of busy pulse during an erase.
tBE
tEPMX
tRA
Maximum read access time. The delay incurred between the DRSHFTsignal going low to the first bit of
data observed at the data register output.
tOE
Delay from OSC_ENAsignal reaching UFM to rising clock of OSCleaving the UFM.
tOSCS
tOSCH
Maximum delay between the OSC_ENArising edge to the ERASE/PROGRAMsignal rising edge.
Minimum delay allowed from the ERASE/PROGRAMsignal going low to the OSC_ENAsignal going
low.
Timing Models
Timing models are simplified block diagrams that illustrate the delays through Altera
devices. Logic can be implemented on different paths. You can trace the actual paths
used in your design by examining the equations listed in the Quartus II Report File
(.rpt) for the project. You can then add up the appropriate internal timing parameters
to estimate the delays through the device.
The MAX II architecture has a globally routed clock. The MultiTrack interconnect
ensures predictable performance, accurate simulation, and accurate timing analysis
across all MAX II device densities and speed grades.
Figure 16–1 shows the timing model for MAX II devices. The timing model is the
preliminary version which is subject to change. The final version of the timing model
will be released once available.
Figure 16–1. MAX II Device Timing Model
Output and Output Enable
Data Delay
tR4
tIODR
tIOE
Data-In/LUT Chain
Output Routing
User
Flash
Memory
Logic Element
LUT Delay
Output
Delay
tOD
tXZ
tZX
tC4
Delay
tLUT
tCOMB
tFASTIO
tCO
tSU
tH
tPRE
tCLR
Input Routing
Delay
I/O Input Delay
Register Control
Delay
I/O Pin
tIN
tDL
tC
From Adjacent LE
tGLOB
INPUT
Combinational Path Delay
I/O Pin
Global Input Delay
To Adjacent LE
Register Delays
Data-Out
MAX II Device Handbook
© October 2008 Altera Corporation
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