16–6
Chapter 16: Understanding Timing in MAX II Devices
Calculating Timing Delays
Figure 16–3. External Timing Parameter (tPD2) Note (1)
TRI
MAX II
Device
LUT
Note to Figure 16–3:
(1) tPD2 = tIN + tDL + tLUT + tCOMB + tFASTIO + (tOD + ΔtOD
)
Figure 16–4. External Timing Parameter (tCO) Note (1), (2)
LE
Register
Notes to Figure 16–4:
(1) tCO = tGLOB + tC + tCO + (N x tR4/4 + M x tC4/4) + (tIODC or tIODR) + (tOD + ΔtOD
)
(2) The constants N and M are subject to change according to the position of the LAB in the entire device.
Figure 16–5. LE Register Clear and Preset Time (tCLR) Note (1)
LE
Register
Note to Figure 16–5:
(1) tCLR = tGLOB + tC + tCLR + (N x tR4/4 + M x tC4/4) + (tIODC or tIODR) + (tOD + ΔtOD
)
Figure 16–6. LE Register Clear and Preset Time (tPRE) Note (1)
LE
Register
Note to Figure 16–6:
(1) tPRE = tGLOB + tLOCAL + tC + tPRE + (N x tR4/4 + M x tC4/4) + (tIODC or tIODR) + (tOD + ΔtOD
)
Setup and Hold Time from an I/O Data and Clock Input
The Quartus II software might insert additional routing delays from the input pin to
the register input to ensure a zero hold time for the LE register. Altera recommends
that you use the Quartus II Timing Analyzer to obtain the setup time and hold time.
See Figure 16–7 and Figure 16–8.
MAX II Device Handbook
© October 2008 Altera Corporation
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