Chapter 16: Understanding Timing in MAX II Devices
16–7
Programmable Input Delay
Figure 16–7. Setup and Hold Time (tSU) Note (1)
LE
Register
Combinational
Logic
Note to Figure 16–7:
(1) tSU = (tIN + N x tR4/4 + M x tC4/4 + tLUT) - (tGLOB + tC) + tSU
Figure 16–8. Setup and Hold Time (tH) Note (1)
LE
Register
Combinational
Logic
Note to Figure 16–8:
(1) tH = (tGLOB + tC) - (tIN + N x tR4/4 + M x tC4/4 + tLUT) + tH
1
For Figure 16–4 through Figure 16–8, the constants N and M are subject to change
according to the position of LAB in the entire device for combinational logic
implementation.
Programmable Input Delay
The programmable input delay provides an option to add a delay to the input pin,
guaranteeing a zero hold time. You can set this option in the Assignment Editor
(Assignments menu) on a pin-by-pin basis. The following procedure shows how to
turn on the input delay for the selected input pin in the Quartus II software:
1. Select input pin name in the design file.
2. Right-click and select Locate in the Assignment Editor.
3. Double-click the cell under Assignment Name and select Input Delay from Pin to
Internal Cells in the pull-down list.
4. Double-click the Value cell to the right of the assignment name just made and
enter 1.
5. On the File menu, click Save.
Timing Model versus Quartus II Timing Analyzer
Hand calculations based on the timing model provide a good estimate of a design’s
performance. However, the Quartus II Timing Analyzer always provides the most
accurate information on design performance because it takes into account secondary
factors that influence the routing microparameters such as:
■
Fan-out for each signal in the delay path
■
Positions of other loads relative to the signal source and destination
© October 2008 Altera Corporation
MAX II Device Handbook
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