Chapter 16: Understanding Timing in MAX II Devices
16–3
Internal Timing Parameters for MAX II UFM
Table 16–2. Internal Timing Microparameters (Part 2 of 2)
Parameter
Description
tIOE
Internal generated output enable delay. The delay from an internally generated signal on the interconnect to
the output enable of the tri-state buffer.
tDL
Input routing delay. The delay incurred from the row I/O pin used as input to the LE adjacent to it.
tIODR
Output data delay for the row interconnect. The delay incurred by signals routed from an interconnect to an
I/O cell.
tOD
Output delay buffer and pad delay. Refer to Timing Model and Specifications section in the DC and
Switching Characteristics chapter in the MAX II Device Handbook for delay adders associated with different
I/O standards, drive strengths, and slew rates.
tXZ
Output buffer disable delay. The delay required for high impedance to appear at the output pin after the
output buffer’s enable control is disabled. Refer to Timing Model and Specifications section in the DC and
Switching Characteristics chapter in the MAX II Device Handbook for delay adders associated with different
I/O standards, drive strengths, and slew rates.
tZX
Output buffer enable delay required for the output signal to appear at the output pin after the tri-state
buffer's enable control is enabled. Refer to Timing Model and Specifications section in the DC and
Switching Characteristics chapter in the MAX II Device Handbook for delay adders associated with different
I/O standards, drive strengths, and slew rates.
tC4
Delay for a column interconnect with average loading. The tC4 covers a distance of four LAB rows.
Delay for a row interconnect with average loading. The tR4 covers a distance of four LAB columns.
Local interconnect delay.
tR4
tLOCAL
Internal Timing Parameters for MAX II UFM
Timing parameters for MAX II user flash memory (UFM) are the timing delays
contributed by the UFM architectural elements, which cannot be measured explicitly.
All timing parameters are shown in italic type. Table 16–3 defines the timing
microparameters for MAX II UFM.
Table 16–3. Internal Timing Microparameters for MAX II UFM (Part 1 of 2)
Parameter
tASU
Description
Address register shift signal setup to address register clock.
Address register shift signal hold from address register clock.
Address register data in setup to address register clock.
Address register data in hold from address register clock.
Data register shift signal setup to data register clock.
tAH
tADS
tADH
tDSS
tDSH
tDDS
tDDH
tDCO
tDP
Data register shift signal hold from data register clock.
Data register data in setup to data register clock.
Data register data in hold from data register clock.
Delay incurred from the data register clock to data register output when shifting the data out.
PROGRAMsignal to data clock hold time.
tPB
Maximum delay between PROGRAMrising edge to UFM BUSYsignal rising edge.
Minimum delay allowed from UFM BUSYsignal going low to PROGRAMsignal going low.
Maximum length of busy pulse during a program.
tBP
tPPMX
tAE
Minimum ERASEsignal to address clock hold time.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
