14–2
Chapter 14: Using Jam STAPL for ISP via an Embedded Processor
Embedded Systems
Figure 14–1. Embedded System Block Diagram
Embedded System
TDI
Interface
Logic
(Optional)
TMS
TCK
TDO
Download Cable
TDI
TMS
TCK
TDO
Control
Control
TDI
8
4
TMS
Any JTAG
Device
d[7..0]
d[3..0]
TCK
20
adr[19..0]
TDO
Embedded
Processor
TDI
Control
EPROM or
System
TMS
MAX II Devices
8
Memory
TCK
d[7..0]
TDO
TDI
20
20
adr[19..0]
adr[19..0]
TMS
Any JTAG
Device
TCK
TDO
Both JTAG connection methods should include space for the MasterBlaster™,
ByteBlaster™ II, or USB-Blaster™ header connection. The header is useful during
prototyping because it allows designers to quickly verify or modify the PLD’s
contents. During production, the header can be removed to decrease cost.
Example Interface PLD Design
Figure 14–2 shows an example design schematic of an interface PLD. A different
design can be implemented; however, important points exemplified in this design are:
■
TMS, TCK, and TDIshould be synchronous outputs
■
Multiplexer logic should be included to allow board access for the MasterBlaster,
ByteBlaster II, or USB-Blaster download cable
1
This design example is for reference only. All of the inputs except data[3..0]are
optional and included only to show how an interface PLD can act as an address
decoder on an embedded data bus.
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
