Chapter 14: Using Jam STAPL for ISP via an Embedded Processor
14–3
Embedded Systems
Figure 14–2. Interface Logic Design Example
data[1..0][2..0]
result[2..0]
LPM_MUX
Byteblaster_nProcessor_Select
TDI_Reg
PR
Q
D
EN
CLR
ByteBlaster_nProcessor_Select
ByteBlaster_TDI
ByteBlaster_TDI
data[0][0]
DATA3
data[1][0]
data[0][1]
data[1][1]
data[0][2]
data[1][2]
TDI_Reg
ByteBlaster_TMS
ByteBlaster_TCK
ByteBlaster_TDO
ByteBlaster_TMS
TMS_Reg
PR
TMS_Reg
D
Q
TDO
EN
CLR
ByteBlaster_TCK
TCK_Reg
DATA2
PR
TCK_Reg
Q
D
address_decode
adr[19..0] AD_VALID
EN
CLR
result0
result1
adr[19..0]
nDS
TDI
TMS
DATA1
DATA0
result2
TCK
TDO
d[3..0]
R_nW
R_AS
CLK
nRESET
In Figure 14–2, the embedded processor asserts the JTAG chain’s address, and the
R_nWand R_ASsignals can be set to tell the interface PLD when the processor wants
to access the chain. A write involves connecting the data path data[3..0]to the
JTAG outputs of the PLD via the three D registers that are clocked by the system clock
(CLK). This clock can be the same clock that the processor uses. Likewise, a read
involves enabling the tri-state buffers and letting the TDOsignal flow back to the
processor. The design also provides a hardware connection to read back the values in
the TDI, TMS, and TCKregisters. This optional feature is useful during the
development phase, allowing software to check the valid states of the registers in the
interface PLD. In addition, multiplexer logic is included to permit a download cable
to program the device chain. This capability is useful during the prototype phase of
development, when programming must be verified.
Board Layout
The following elements are important when laying out a board that programs via the
IEEE Std. 1149.1 JTAG chain:
■
Treat the TCKsignal trace as a clock tree
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
