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EPM240T100C5 参数 Datasheet PDF下载

EPM240T100C5图片预览
型号: EPM240T100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [最大II器件]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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13–16  
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices  
Disabling IEEE Std. 1149.1 BST Circuitry  
Disabling IEEE Std. 1149.1 BST Circuitry  
The IEEE Std. 1149.1 BST circuitry for MAX II devices is enabled upon device power-  
up. Because this circuitry may be used for BST or ISP, this circuitry must be enabled  
only if these features are used. This section describes how to disable the IEEE Std.  
1149.1 circuitry to ensure that the circuitry is not inadvertently enabled when it is not  
needed.  
Table 13–3 shows the pin connections necessary for disabling JTAG in MAX II devices  
that have dedicated IEEE Std. 1149.1 pins.  
Table 13–3. Disabling IEEE Std. 1149.1 Circuitry  
JTAG Pins (1)  
TMS  
TCK  
TDI  
TDO  
VCC(2)  
GND(3)  
VCC(2)  
Leave Open  
Notes to Table 13–3:  
(1) There is no software option to disable JTAG in MAX II devices. The JTAG pins are dedicated.  
(2) VCC refers to VCCIO of Bank 1.  
(3) The TCKsignal may also be tied high. If TCK is tied high, power-up conditions must ensure that TMSis pulled  
high before TCK. Pulling TCKlow avoids this power-up condition.  
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing  
Use the following guidelines when performing boundary-scan testing with IEEE Std.  
1149.1 devices:  
If a pattern (for example, a 10-bit 1010101010pattern) does not shift out of the  
instruction register via the TDOpin during the first clock cycle of the SHIFT_IR  
state, the proper TAP controller state has not been reached. To solve this problem,  
try one of the following procedures:  
Verify that the TAP controller has reached the SHIFT_IRstate correctly. To  
advance the TAP controller to the SHIFT_IRstate, return to the RESETstate  
and clock the code 01100on the TMS pin.  
Check the connections to the VCC, GND, and JTAG pins on the device.  
Perform a SAMPLE/PRELOADtest cycle prior to the first EXTESTtest cycle to  
ensure that known data is present at the device pins when the EXTESTmode is  
entered. If the OEJupdate register contains a 0, the data in the OUTJupdate  
register will be driven out. The state must be known and correct to avoid  
contention with other devices in the system.  
Do not perform EXTESTand SAMPLE/PRELOADtests during ISP. These  
instructions are supported before and after ISP but not during ISP.  
1
If problems persist, contact Altera Applications.  
MAX II Device Handbook  
© October 2008 Altera Corporation  
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