14. Using Jam STAPL for ISP via an
Embedded Processor
MII51015-1.8
Introduction
Advances in programmable logic devices (PLDs) have enabled the innovative in-
system programmability (ISP) feature. The Jam™ Standard Test and Programming
Language (STAPL), JEDEC standard JESD-71, is compatible with all current PLDs that
offer ISP via Joint Test Action Group (JTAG), providing a software-level, vendor-
independent standard for in-system programming and configuration. Designers who
use Jam STAPL to implement ISP enhance the quality, flexibility, and life-cycle of their
end products. Regardless of the number of PLDs that must be programmed or
configured, Jam STAPL simplifies in-field upgrades and revolutionizes the
programming of PLDs.
®
This chapter describes MAX II device programming support using Jam STAPL in
embedded systems.
This chapter contains the following sections:
■
■
■
“Embedded Systems” on page 14–1
“Software Development” on page 14–4
“Updating Devices Using Jam” on page 14–14
Embedded Systems
All embedded systems are made up of both hardware and software components.
When designing an embedded system, the first step is to layout the printed circuit
board (PCB). The second step is to develop the firmware that manages the board’s
functionality.
Connecting the JTAG Chain to the Embedded Processor
There are two ways to connect the JTAG chain to the embedded processor. The most
straightforward method is to connect the embedded processor directly to the JTAG
chain. In this method, four of the processor pins are dedicated to the JTAG interface,
thereby saving board space but reducing the number of available embedded
processor pins.
Figure 14–1 illustrates the second method, which is to connect the JTAG chain to an
existing bus via an interface PLD. In this method, the JTAG chain becomes an address
on the existing bus. The processor then reads from or writes to the address
representing the JTAG chain.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
