14–4
Chapter 14: Using Jam STAPL for ISP via an Embedded Processor
Software Development
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Use a pull-down resistor on TCK
Make the JTAG signal traces as short as possible
Add external resistors to pull outputs to a defined logic level
TCK Signal Trace Protection and Integrity
TCKis the clock for the entire JTAG chain of devices. These devices are edge-triggered
on the TCKsignal, so it is imperative that TCKis protected from high-frequency noise
and has good signal integrity. Ensure that the signal meets the rise time (tR) and fall
time (tF) parameters in the appropriate device family data sheet. The signal may also
need termination to prevent overshoot, undershoot, or ringing. This step is often
overlooked since this signal is software-generated and originates at a processor
general-purpose I/O pin.
Pull-Down Resistors on TCK
TCKshould be held low via a pull-down resistor to keep the JTAG Test Access Port
(TAP) in a known state at power-up. A missing pull-down resistor can cause a device
to power-up in a JTAG BST state, which may cause conflicts on the board. A typical
resistor value is 1 kΩ.
JTAG Signal Traces
Short JTAG signal traces help eliminate noise and drive-strength issues. Special
attention should be paid to the TCKand TMSpins. Because TCKand TMSare connected
to every device in the JTAG chain, these traces will see higher loading than TDIor
TDO. Depending on the length and loading of the JTAG chain, some additional
buffering may be required to ensure that the signals propagate to and from the
processor with integrity.
External Resistors
You should add external resistors to output pins to pull outputs to a defined logic
level during programming. Output pins will tri-state during programming. Also, on
®
MAX II devices, the pins will be pulled up by a weak internal resistor. Altera
recommends that outputs driving sensitive input pins be tied to the appropriate level
by an external resistor.
Each preceding board layout element may require further analysis, especially signal
integrity. In some cases, you may need to analyze the loading and layout of the JTAG
chain to determine whether to use discrete buffers or a termination technique.
f
For more information, refer to the In-System Programmability Guidelines for MAX II
Devices chapter in the MAX II Device Handbook.
Software Development
®
Altera’s embedded programming uses the Jam file output from the Quartus II
software tool with the standardized Jam Player software. Designing these tools
requires minimal developer intervention because Jam files contain all of the data for
programming MAX II devices. The bulk of development time is spent porting the Jam
Player to the host embedded processor.
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
