Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
13–7
IEEE Std. 1149.1 BST Operation Control
Figure 13–5. IEEE Std. 1149.1 TAP Controller State Machine
TEST_LOGIC/
TMS = 1
TMS = 0
RESET
TMS = 0
TMS = 1
RUN_TEST/
IDLE
TMS = 1
TMS = 0
SELECT_IR_SCAN
SELECT_DR_SCAN
TMS = 1
TMS = 0
TMS = 1
TMS = 1
CAPTURE_DR
CAPTURE_IR
TMS = 0
TMS = 0
SHIFT_DR
SHIFT_IR
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 1
EXIT1_DR
EXIT1_IR
TMS = 0
TMS = 0
PAUSE_DR
PAUSE_IR
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 0
EXIT2_DR
EXIT2_IR
TMS = 1
TMS = 1
TMS = 1
TMS = 1
UPDATE_DR
UPDATE_IR
TMS = 0
TMS = 0
When the TAP controller is in the TEST_LOGIC/RESETstate, the BST circuitry is
disabled, the device is in normal operation, and the instruction register is initialized
with IDCODEas the initial instruction. At device power-up, the TAP controller starts
in this TEST_LOGIC/RESETstate. In addition, the TAP controller may be forced to the
TEST_LOGIC/RESETstate by holding TMShigh for five TCKclock cycles. Once in the
TEST_LOGIC/RESETstate, the TAP controller remains in this state as long as TMS
continues to be held high while TCKis clocked. Figure 13–6 shows the timing
requirements for the IEEE Std. 1149.1 signals.
© October 2008 Altera Corporation
MAX II Device Handbook
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