13–8
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
IEEE Std. 1149.1 BST Operation Control
Figure 13–6. IEEE Std. 1149.1 Timing Waveforms (Note 1)
TMS
TDI
t
JCP
t
t
JPH
JPSU
t
t
JCL
JCH
TCK
TDO
t
t
t
JPZX
JSZX
JPCO
JPXZ
t
t
JSH
JSSU
Signal
to Be
Captured
t
t
t
JSXZ
JSCO
Signal
to Be
Driven
Note to Figure 13–6:
(1) For timing parameter values, refer to theDC and Switching Characteristics chapter in the MAX II Device Handbook.
To start IEEE Std. 1149.1 operation, select an instruction mode by advancing the TAP
controller to the shift instruction register (SHIFT_IR) state and shift in the
appropriate instruction code on the TDIpin. The waveform diagram in Figure 13–7
represents the entry of the instruction code into the instruction register. It shows the
values of TCK, TMS, TDI, and TDOand the states of the TAP controller. From the
RESET state, TMS is clocked with the pattern 01100 to advance the TAP controller to
SHIFT_IR.
Figure 13–7. Selecting the Instruction Mode
TCK
TMS
TDI
TDO
SHIFT_IR
TAP_STATE
SELECT_IR_SCAN
RUN_TEST/IDLE
SELECT_DR_SCAN
EXIT1_IR
CAPTURE_IR
TEST_LOGIC/RESET
The TDOpin is tri-stated in all states except the SHIFT_IRand SHIFT_DRstates. The
TDOpin is activated at the first falling edge of TCKafter entering either of the shift
states and is tri-stated at the first falling edge of TCKafter leaving either of the shift
states.
When the SHIFT_IRstate is activated, TDOis no longer tri-stated, and the initial state
of the instruction register is shifted out on the falling edge of TCK. TDOcontinues to
shift out the contents of the instruction register as long as the SHIFT_IRstate is
active. The TAP controller remains in the SHIFT_IRstate as long as TMSremains low.
MAX II Device Handbook
© October 2008 Altera Corporation
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