Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
13–3
IEEE Std. 1149.1 Boundary-Scan Register
Figure 13–2 shows a functional model of the IEEE Std. 1149.1 circuitry.
Figure 13–2. IEEE Std. 1149.1 Circuitry
Instruction Register
TDI
TDO
UPDATEIR
CLOCKIR
SHIFTIR
Instruction Decode
TAP
TMS
TCK
Controller
Data Registers
Bypass Register
UPDATEDR
CLOCKDR
SHIFTDR
Boundary-Scan Register (1)
a
Device ID Register
ISP Registers
Note to Figure 13–2:
(1) Refer to the JTAG and In-System Programmability chapter in the MAX II Device Handbook for the boundary-scan register length in MAX II devices.
IEEE Std. 1149.1 boundary-scan testing is controlled by a TAP controller, which is
described in “IEEE Std. 1149.1 BST Operation Control” on page 13–6. The TMS and
TCKpins operate the TAP controller, and the TDIand TDOpins provide the serial path
for the data registers. The TDIpin also provides data to the instruction register, which
then generates control logic for the data registers.
IEEE Std. 1149.1 Boundary-Scan Register
The boundary-scan register is a large serial shift register that uses the TDIpin as an
input and the TDOpin as an output. The boundary-scan register consists of 3-bit
peripheral elements that are associated with I/O pins of the MAX II devices. You can
use the boundary-scan register to test external pin connections or to capture internal
data.
f
Refer to the JTAG and In-System Programmability chapter in the MAX II Device Handbook
for the boundary-scan register length of MAX II devices.
© October 2008 Altera Corporation
MAX II Device Handbook
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