Timing Model and Specifications
Performance
Table 5–14 shows the MAX II device performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of megafunctions. Performance values for –3, –4,
and –5 speed grades are based on an EPM1270 device target while –6 and
–7 speed grades are based on an EPM570Z device target.
Table 5–14. MAX II Device Performance
Resources Used
Performance
–5
Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade
Resource Design Size and
–3
–4
–6
–7
Unit
UFM
Used
Function
Mode
LEs
Blocks
LE
16-bit counter (1)
64-bit counter (1)
—
—
—
16
64
11
0
0
0
304.0
201.5
6.0
247.5
154.8
8.0
201.1
125.8
9.3
184.1
83.2
17.4
123.5
83.2
17.3
MHz
MHz
ns
16-to-1
multiplexer
32-to-1
multiplexer
—
—
—
24
5
0
0
0
7.1
5.1
5.2
9.0
6.6
6.6
11.4
8.2
12.5
9.0
22.8
15.0
15.0
ns
ns
ns
16-bit XOR
function
16-bit decoder
with single
5
8.2
9.2
address line
UFM
512 × 16
512 × 16
512 × 8
None
3
1
1
1
10.0
8.0
(4)
10.0
8.0
(4)
10.0
8.0
(4)
10.0
9.7
(4)
10.0
9.7
(4)
MHz
MHz
MHz
SPI (2)
37
73
Parallel
(3)
I2C (3)
512 × 16
142
1
100 (5) 100 (5) 100 (5) 100 (5) 100 (5) kHz
Notes to Table 5–14:
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number
of LEs used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I2C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
5–12Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
July 2008
ALTERA [ ALTERA CORPORATION ]
