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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
MultiVolt I/O Interface  
The MAX II architecture supports the MultiVolt I/O interface feature,  
which allows MAX II devices in all packages to interface with systems of  
different supply voltages. The devices have one set of VCCpins for  
internal operation (VCCINT), and up to four sets for input buffers and I/O  
output driver buffers (VCCIO), depending on the number of I/O banks  
available in the devices where each set of VCC pins powers one I/O bank.  
The EPM240 and EPM570 devices have two I/O banks respectively while  
the EPM1270 and EPM2210 devices have four I/O banks respectively.  
Connect VCCIOpins to either a 1.5-V, 1.8 V, 2.5-V, or 3.3-V power supply,  
depending on the output requirements. The output levels are compatible  
with systems of the same voltage as the power supply (that is, when  
VCCIOpins are connected to a 1.5-V power supply, the output levels are  
compatible with 1.5-V systems). When VCCIOpins are connected to a  
3.3-V power supply, the output high is 3.3 V and is compatible with 3.3-V  
or 5.0-V systems. Table 2–7 summarizes MAX II MultiVolt I/O support.  
Table 2–7. MAX II MultiVolt I/O Support Note (1)  
Input Signal  
Output Signal  
VCCIO (V)  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
5.0 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
5.0 V  
v
v
v
v
v
v
v
v
v
1.5  
1.8  
2.5  
3.3  
v
v
v
v (2)  
v (3)  
v (6)  
v
v (3)  
v (6)  
v
v (6)  
v (4)  
v (5)  
v
v (7)  
Notes to Table 2–7:  
(1) To drive inputs higher than VCCIO but less than 4.0 V including the overshoot, disable the PCI clamping diode.  
However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V.  
(2) When VCCIO = 1.8 V, a MAX II device can drive a 1.5-V device with 1.8-V tolerant inputs.  
(3) When VCCIO = 2.5 V, a MAX II device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.  
(4) When VCCIO = 3.3 V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger  
than expected.  
(5) MAX II devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode on the  
EPM1270 and EPM2210 devices.  
(6) When VCCIO = 3.3 V, a MAX II device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.  
(7) When VCCIO = 3.3 V, a MAX II device can drive a device with 5.0-V TTL inputs but not 5.0-V CMOS inputs. In the  
case of 5.0-V CMOS, open-drain setting with internal PCI clamp diode (available only on EPM1270 and EPM2210  
devices) and external resistor is required.  
f
For information about output pin source and sink current guidelines,  
refer to the AN 428: MAX II CPLD Design Guidelines.  
2–40Core Version a.b.c variable  
MAX II Device Handbook, Volume 1  
Altera Corporation  
March 2008  
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