Chapter 3. JTAG and
In-System Programmability
MII51003-1.5
This chapter discusses how to use the IEEE Standard 1149.1
Boundary-Scan Test (BST) circuitry in MAX II devices and includes the
following sections:
Introduction
■
■
“IEEE Std. 1149.1 (JTAG) Boundary-Scan Support” on page 3–1
“In System Programmability” on page 3–5
All MAX® II devices provide Joint Test Action Group (JTAG)
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
boundary-scan test (BST) circuitry that complies with the IEEE Std.
1149.1-2001 specification. JTAG boundary-scan testing can only be
performed at any time after VCCINT and all VCCIO banks have been fully
powered and a tCONFIG amount of time has passed. MAX II devices can
also use the JTAG port for in-system programming together with either
the Quartus® II software or hardware using Programming Object Files
TM
(.pof), Jam Standard Test and Programming Language (STAPL) Files
(.jam), or Jam Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard are determined by the VCCIO of the
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in Table 3–1.
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
EXTEST(1)
00 0000 1111
11 1111 1111
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDIand TDO
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation.
Altera Corporation
December 2007
3–1
ALTERA [ ALTERA CORPORATION ]
