I/O Structure
PCI Compliance
The MAX II EPM1270 and EPM2210 devices are compliant with PCI
applications as well as all 3.3-V electrical specifications in the PCI Local
Bus Specification Revision 2.2. These devices are also large enough to
support PCI intellectual property (IP) cores. Table 2–5 shows the MAX II
device speed grades that meet the PCI timing specifications.
Table 2–5. MAX II Devices and Speed Grades that Support 3.3-V PCI Electrical Specifications
and Meet PCI Timing
Device
33-MHz PCI
66-MHz PCI
EPM1270
EPM2210
All Speed Grades
All Speed Grades
–3 Speed Grade
–3 Speed Grade
Schmitt Trigger
The input buffer for each MAX II device I/O pin has an optional Schmitt
trigger setting for the 3.3-V and 2.5-V standards. The Schmitt trigger
allows input buffers to respond to slow input edge rates with a fast
output edge rate. Most importantly, Schmitt triggers provide hysteresis
on the input buffer, preventing slow-rising noisy input signals from
ringing or oscillating on the input signal driven into the logic array. This
provides system noise tolerance on MAX II inputs, but adds a small,
nominal input delay.
The JTAG input pins (TMS, TCK, and TDI) have Schmitt trigger buffers
that are always enabled.
1
The TCK input is susceptible to high pulse glitches when the
input signal fall time is greater than 200 ns for all I/O standards.
Output Enable Signals
Each MAX II IOE output buffer supports output enable signals for
tri-state control. The output enable signal can originate from the
GCLK[3..0]global signals or from the MultiTrack interconnect. The
MultiTrack interconnect routes output enable signals and allows for a
unique output enable for each output or bidirectional pin.
2–36Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
March 2008
ALTERA [ ALTERA CORPORATION ]
