欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM1270GT144I4N的Datasheet PDF文件第42页浏览型号EPM1270GT144I4N的Datasheet PDF文件第43页浏览型号EPM1270GT144I4N的Datasheet PDF文件第44页浏览型号EPM1270GT144I4N的Datasheet PDF文件第45页浏览型号EPM1270GT144I4N的Datasheet PDF文件第47页浏览型号EPM1270GT144I4N的Datasheet PDF文件第48页浏览型号EPM1270GT144I4N的Datasheet PDF文件第49页浏览型号EPM1270GT144I4N的Datasheet PDF文件第50页  
I/O Structure  
Table 2–6. Programmable Drive Strength Note (1) (Part 2 of 2)  
I
OH/IOL Current Strength Setting (mA)  
I/O Standard  
1.5-V LVCMOS  
4
2
Note to Table 2–6:  
(1) The IOH current strength numbers shown are for a condition of a VOUT = VOH  
minimum, where the VOH minimum is specified by the I/O standard. The IOL  
current strength numbers shown are for a condition of a VOUT = VOL maximum,  
where the VOL maximum is specified by the I/O standard. For 2.5-V  
LVTTL/LVCMOS, the IOH condition is VOUT = 1.7 V and the IOL condition is  
VOUT = 0.7 V.  
Slew-Rate Control  
The output buffer for each MAX II device I/O pin has a programmable  
output slew-rate control that can be configured for low noise or  
high-speed performance. A faster slew rate provides high-speed  
transitions for high-performance systems. However, these fast transitions  
may introduce noise transients into the system. A slow slew rate reduces  
system noise, but adds a nominal output delay to rising and falling edges.  
The lower the voltage standard (for example, 1.8-V LVTTL) the larger the  
output delay when slow slew is enabled. Each I/O pin has an individual  
slew-rate control, allowing the designer to specify the slew rate on a  
pin-by-pin basis. The slew-rate control affects both the rising and falling  
edges.  
Open-Drain Output  
MAX II devices provide an optional open-drain (equivalent to  
open-collector) output for each I/O pin. This open-drain output enables  
the device to provide system-level control signals (for example, interrupt  
and write enable signals) that can be asserted by any of several devices.  
This output can also provide an additional wired-OR plane.  
Programmable Ground Pins  
Each unused I/O pin on MAX II devices can be used as an additional  
ground pin. This programmable ground feature does not require the use  
of the associated LEs in the device. In the Quartus II software, unused  
pins can be set as programmable GND on a global default basis or they  
can be individually assigned. Unused pins also have the option of being  
set as tri-stated input pins.  
2–38Core Version a.b.c variable  
MAX II Device Handbook, Volume 1  
Altera Corporation  
March 2008  
 复制成功!