MAX II Architecture
MAX II devices also provide a chip-wide output enable pin (DEV_OE) to
control the output enable for every output pin in the design. An option
set before compilation in the Quartus II software controls this pin. This
chip-wide output enable uses its own routing resources and does not use
any of the four global resources. If this option is turned on, all outputs on
the chip operate normally when DEV_OEis asserted. When the pin is
deasserted, all outputs are tri-stated. If this option is turned off, the
DEV_OEpin is disabled when the device operates in user mode and is
available as a user I/O pin.
Programmable Drive Strength
The output buffer for each MAX II device I/O pin has two levels of
programmable drive strength control for each of the LVTTL and
LVCMOS I/O standards. Programmable drive strength provides system
noise reduction control for high performance I/O designs. Although a
separate slew-rate control feature exists, using the lower drive strength
setting provides signal slew-rate control to reduce system noise and
signal overshoot without the large delay adder associated with the
slew-rate control feature. Table 2–6 shows the possible settings for the
I/O standards with drive strength control. The Quartus II software uses
the maximum current strength as the default setting. The PCI I/O
standard is always set at 20 mA with no alternate setting.
Table 2–6. Programmable Drive Strength Note (1) (Part 1 of 2)
IOH/IOL Current Strength Setting (mA)
I/O Standard
3.3-V LVTTL
16
8
3.3-V LVCMOS
8
4
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
14
7
6
3
Altera Corporation
March 2008
2–37
MAX II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
