FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 32. LE Timing Microparameters (Part 2 of 2)
Symbol
Note (1)
Parameter
Conditions
tSU
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
tH
LE register hold time for data and enable signals after clock
LE register preset delay
tPRE
tCLR
tCH
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
tCL
Table 33. IOE Timing Microparameters
Note (1)
Parameter
Symbol
Conditions
tIOD
IOE data delay
IOE register control signal delay
tIOC
tIOCO
tIOCOMB
tIOSU
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
tIOH
IOE register hold time for data and enable signals after clock
IOE register clear time
tIOCLR
tOD1
tOD2
tOD3
tXZ
Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT
Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
tZX1
IOE output buffer enable delay, slow slew rate = off, VCCIO = VCCINT
IOE output buffer enable delay, slow slew rate = off, VCCIO = low voltage
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
tZX2
tZX3
tINREG
tIOFD
tINCOMB
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
60
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