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EPF10K30RC208-3 参数 Datasheet PDF下载

EPF10K30RC208-3图片预览
型号: EPF10K30RC208-3
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式可编程逻辑器件系列 [Embedded Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 128 页 / 1975 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 10K Embedded Programmable Logic Device Family Data Sheet  
Table 36. Interconnect Timing Microparameters  
Note (1)  
Symbol Parameter  
Conditions  
tDIN2IOE  
Delay from dedicated input pin to IOE control input  
Delay from dedicated clock pin to LE or EAB clock  
Delay from dedicated input or clock to LE or EAB data  
Delay from dedicated clock pin to IOE clock  
(7)  
(7)  
(7)  
(7)  
(7)  
tDCLK2LE  
tDIN2DATA  
tDCLK2IOE  
tDIN2LE  
Delay from dedicated input pin to LE or EAB control input  
Routing delay for an LE driving another LE in the same LAB  
tSAMELAB  
tSAMEROW  
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7)  
same row  
tSAMECOLUMN Routing delay for an LE driving an IOE in the same column  
(7)  
tDIFFROW  
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7)  
row  
tTWOROWS  
tLEPERIPH  
Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7)  
Routing delay for an LE driving a control signal of an IOE via the peripheral (7)  
control bus  
tLABCARRY  
tLABCASC  
Routing delay for the carry-out signal of an LE driving the carry-in signal of a  
different LE in a different LAB  
Routing delay for the cascade-out signal of an LE driving the cascade-in  
signal of a different LE in a different LAB  
Table 37. External Timing Parameters  
Notes (8), (10)  
Symbol  
Parameter  
Conditions  
tDRR  
Register-to-register delay via four LEs, three row interconnects, and four local (9)  
interconnects  
tINSU  
tINH  
Setup time with global clock at IOE register  
Hold time with global clock at IOE register  
tOUTCO  
Clock-to-output delay with global clock at IOE register  
Table 38. External Bidirectional Timing Parameters  
Note (10)  
Symbol  
Parameter  
Condition  
tINSUBIDIR  
tINHBIDIR  
tOUTCOBIDIR  
tXZBIDIR  
Setup time for bidirectional pins with global clock at adjacent LE register  
Hold time for bidirectional pins with global clock at adjacent LE register  
Clock-to-output delay for bidirectional pins with global clock at IOE register  
Synchronous IOE output buffer disable delay  
tZXBIDIR  
Synchronous IOE output buffer enable delay, slow slew rate = off  
Altera Corporation  
63  
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