FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
OE Register
PRN
D
Q
Dedicated
Clock
t
t
XZBIDIR
ZXBIDIR
CLRN
t
OUTCOBIDIR
Output Register
PRN
Bidirectional
Pin
D
Q
t
t
INSUBIDIR
CLRN
INHBIDIR
Input Register
PRN
D
Q
CLRN
Tables 32 through 36 describe the FLEX 10K device internal timing
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis. Tables 37 through 38 describe FLEX 10K external
timing parameters.
Table 32. LE Timing Microparameters (Part 1 of 2)
Note (1)
Symbol Parameter
Conditions
tLUT
LUT delay for data-in
LUT delay for carry-in
tCLUT
tRLUT
tPACKED
tEN
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
tCICO
tCGEN
tCGENR
tCASC
tC
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
tCO
tCOMB
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