FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 23. Output Drive Characteristics for EPF10K250A Device
50
40
30
20
50
40
30
IOL
IOL
VCCINT = 3.3 V
VCCIO = 3.3 V
Room Temperature
VCCINT = 3.3 V
VCCIO = 2.5 V
Room Temperature
Typical I
Output
Current (mA)
Typical I
Output
Current (mA)
O
O
20
10
IOH
10
IOH
1
2
3
4
1
2
3
4
VO Output Voltage (V)
VO Output Voltage (V)
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Timing Model
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■
■
■
■
LE register clock-to-output delay (tCO
Interconnect delay (tSAMEROW
LE look-up table delay (tLUT
LE register setup time (tSU
)
)
)
)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Altera Corporation
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