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EPC16QI100 参数 Datasheet PDF下载

EPC16QI100图片预览
型号: EPC16QI100
PDF下载: 下载PDF文件 查看货源
内容描述: 2.增强型配置器件( EPC4 , EPC8和EPC16 )数据表 [2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet]
分类和应用: PC
文件页数/大小: 36 页 / 387 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Pin Description  
Table 2–8. External Flash Interface Pins (Part 1 of 2)  
Pin Name  
Pin Type  
Description  
A[20..0]  
Input  
These pins are the address input to the flash memory for read and write  
operations. The addresses are internally latched during a write cycle.  
When the external flash interface is not used, leave these pins floating  
(with the few exceptions noted below). These flash address, data, and  
control pins are internally connected to the configuration controller.  
In the 100-pin PQFP package, four address pins (A0, A1, A15, A16) are  
not internally connected to the controller. These loop back connections  
must be made on the board between the C-A[]and F-A[]pins even  
when not using the external flash interface. All other address pins are  
connected internal to the package.  
All address pins are connected internally in the 88-pin Ultra FineLine BGA  
package.  
Pin A20in EPC16 devices, pins A20and A19in EPC8 devices, and pins  
A20, A19, and A18in EPC4 devices are no-connects. These pins should  
be left floating on the board.  
DQ[15..0]  
Bidirectional  
This is the flash data bus interface between the flash memory and the  
controller. The controller or an external source drives DQ[15..0]during  
the flash command and the data write bus cycles. During the data read  
cycle, the flash memory drives the DQ[15..0]to the controller or  
external device.  
Leave these pins floating on the board when the external flash interface is  
not used.  
CE#  
Input  
Input  
Active low flash input pin that activates the flash memory when asserted.  
When it is high, it deselects the device and reduces power consumption  
to standby levels. This flash input pin is internally connected to the  
controller.  
Leave this pin floating on the board when the external flash interface is not  
used.  
RP# (1)  
Active low flash input pin that resets the flash when asserted. When high,  
it enables normal operation. When low, it inhibits write operation to the  
flash memory, which provides data protection during power transitions.  
This flash input is not internally connected to the controller. Hence, an  
external loop back connection between C-RP#and F-RP#must be made  
on the board even when you are not using the external flash interface.  
When using the external flash interface, connect the external device to the  
RP#pin with the loop back.  
2–22  
Altera Corporation  
August 2005  
Configuration Handbook, Volume 2  
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