Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
The enhanced configuration device supports a programmable POR delay
setting. You can set the POR delay to the default 100-ms setting or reduce
the POR delay to 2 ms for systems that require fast power-up. The
PORSELinput pin controls this POR delay; a logic high level selects the
2-ms delay, while a logic low level selects the 100-ms delay.
The enhanced configuration device can enter reset under the following
conditions:
■
The POR reset starts at initial power-up during VCC ramp-up or if
VCC drops below the minimum operating condition anytime after
VCC has stabilized
■
■
The FPGA initiates reconfiguration by driving nSTATUSlow, which
occurs if the FPGA detects a CRC error or if the FPGA’s nCONFIG
input pin is asserted
The controller detects a configuration error and asserts OEto initiate
re-configuration of the Altera FPGA (for example when CONF_DONE
stays low after all configuration data has been transmitted)
Altera requires that you power-up the FPGA's VCCINT supply before the
enhanced configuration device's POR expires.
Power
Sequencing
Power up needs to be controlled so that the enhanced configuration
device’s OEsignal goes high after the CONF_DONEsignal is pulled low. If
the EEPC device exits POR before the FPGA is powered up, the
CONF_DONEsignal will be high since the pull-up resistor is holding this
signal high. When the enhanced configuration device exits POR, OEis
released and pulled high by a pull-up resistor. Since the enhanced
configuration device samples the nCSsignal on the rising edge of OE, it
detects a high level on CONF_DONEand enters an idle mode. DATAand
DCLKoutputs will not toggle in this state and configuration will not
begin. The enhanced configuration device will only exit this mode if it is
powered down and then powered up correctly.
1
To ensure the enhanced configuration device enters
configuration mode properly, you need to ensure that the FPGA
completes power-up before the enhanced configuration device
exits POR.
The pin-selectable POR time feature is useful for ensuring this power-up
sequence. The enhanced configuration device has two POR settings, 2 ms
when PORSELis set to a high level and 100 ms when PORSELis set to a
low level. For more margin, the 100-ms setting can be selected to allow the
FPGA to power-up before configuration is attempted.
Altera Corporation
August 2005
2–25
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
