Functional Description
Programmable Configuration Clock
The configuration clock (DCLK) speed is user programmable. One of two
clock sources can be used to synthesize the configuration clock; a
programmable oscillator or an external clock input pin (EXCLK). The
configuration clock frequency can be further synthesized using the clock
divider circuitry. This clock can be divided by the N counter to generate
your DCLKoutput. The N divider supports all integer dividers between
1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all
clock divisions other than non-integer divisions is 50% (for the non-
integer dividers, the duty cycle will not be 50%). See Figure 2–5 for a block
diagram of the clock divider unit.
Figure 2–5. Clock Divider Unit
Configuration Device
Clock Divider Unit
External Clock
(Up to 133 MHz)
Divide
DCLK
by N
10 MHz
33 MHz
50 MHz
66 MHz
Internal Oscillator
The DCLKfrequency is limited by the maximum DCLKfrequency the
FPGA supports.
f
The maximum DCLKinput frequency supported by the FPGA is
specified in the appropriate FPGA family chapter in the Configuration
Handbook.
2–18
Altera Corporation
Configuration Handbook, Volume 2
August 2005
ALTERA [ ALTERA CORPORATION ]
