Power-On Reset (POR)
Table 2–9. JTAG Interface Pins and Other Required Controller Pins
Pin Name
Pin Type
Description
TDI
Input
This is the JTAG data input pin.
Connect this pin to VCC if the JTAG circuitry is not used.
This is the JTAG data output pin.
TDO
Output
Input
Input
Input
Do not connect this pin if the JTAG circuitry is not used (leave floating).
This is the JTAG clock pin.
TCK
Connect this pin to GND if the JTAG circuitry is not used.
This is the JTAG mode select pin.
TMS
Connect this pin to VCC if the JTAG circuitry is not used.
PGM[2..0]
These three input pins select one of the eight pages of configuration data
to configure the FPGA(s) in the system.
Connect these pins on the board to select the page specified in the
Quartus II software when generating the enhanced configuration device
POF. PGM[2]is the MSB. Default selection is page 0; PGM[2..0]=000.
These pins must not be left floating.
EXCLK
Input
Input
Optional external clock input pin that can be used to generate the
configuration clock (DCLK).
When an external clock source is not used, connect this pin to a valid logic
level (high or low) to prevent a floating input buffer.
PORSEL
This pin selects a 2-ms or 100-ms POR counter delay during power up.
When PORSELis low, POR time is 100-ms. When PORSELis high, POR
time is 2 ms.
This pin must be connected to a valid logic level.
TM0
TM1
Input
Input
For normal operation, this test pin must be connected to GND.
For normal operating, this test pin must be connected to VCC
.
The POR circuit keeps the system in reset until power supply voltage
levels have stabilized. The POR time consists of the VCC ramp time and a
user programmable POR delay counter. When the supply is stable and
the POR counter expires, the POR circuit releases the OEpin. The POR
time can be further extended by an external device by driving the OEpin
low.
Power-On Reset
(POR)
1
Do not execute JTAG or ISP instructions until POR is complete.
2–24
Altera Corporation
August 2005
Configuration Handbook, Volume 2