Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
The controller chip features a programmable oscillator that can output
four different frequencies. The various settings generate clock outputs at
frequencies as high as 10, 33, 50, and 66 MHz, as shown in Table 2–6.
Table 2–6. Internal Oscillator Frequencies
Frequency Setting
Min (MHz)
Typ (MHz)
Max (MHz)
10
33
50
66
6.4
8.0
10.0
33.0
50.0
66.0
21.0
32.0
42.0
26.5
40.0
53.0
Clock source, oscillator frequency, and clock divider (N) settings can be
made in the Quartus II software, by accessing the Configuration Device
Options inside the Device Settings window or the Convert
Programming Files window. The same window can be used to select
between the internal oscillator and the external clock (EXCLK) input pin
as your configuration clock source. The default setting selects the internal
oscillator at the 10 MHz setting as the clock source, with a divide factor
of 1.
f
For more information on making the configuration clock source,
frequency, and divider settings, refer to Using Altera Enhanced
Configuration Devices, chapter 3 in volume 2 of the Configuration
Handbook.
Flash In-System Programming (ISP)
The flash memory inside enhanced configuration devices can be
programmed in-system via the JTAG interface and the external flash
interface. JTAG-based programming is facilitated by the configuration
controller in the enhanced configuration device. External flash interface
programming requires an external processor or FPGA to control the flash.
1
The enhanced configuration device flash memory supports
100,000 erase cycles.
JTAG-based Programming
The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in enhanced
configuration devices to facilitate the testing of its interconnection and
functionality. Enhanced configuration devices also support the ISP mode.
The enhanced configuration device is compliant with the IEEE Std. 1532
draft 2.0 specification.
Altera Corporation
August 2005
2–19
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
