Functional Description
The JTAG unit of the configuration controller communicates directly with
the flash memory. The controller processes the ISP instructions and
performs the necessary flash operations. The enhanced configuration
devices support a maximum JTAG TCKfrequency of 10 MHz.
During JTAG-based ISP, the external flash interface is not available.
Before the JTAG interface programs the flash memory, an optional JTAG
instruction (PENDCFG) can be used to assert the FPGA’s nCONFIGpin
(via the nINIT_CONFpin). This will keep the FPGA in reset and
terminate any internal flash access. This function prevents contention on
the flash pins when both JTAG ISP and an external FPGA/processor try
to access the flash simultaneously. The nINIT_CONFpin is released when
the Initiate Configuration (nINIT_CONF) JTAG instruction is updated.
As a result, the FPGA is configured with the new configuration data
stored in flash.
This function can be added to your programming file in the Quartus II
software by enabling the Initiate configuration after programming
option in the Programmer options window (Options menu).
Programming via External Flash Interface
This method allows parallel programming of the flash memory (using the
16-bit data bus). An external processor or FPGA acts as the flash
controller and has access to programming data (via a communication link
such as UART, Ethernet, and PCI). In addition to the program, erase, and
verify operations, the external flash interface supports block/sector
protection instructions.
f
For information on protection commands, areas, and lock bits, refer to
the appropriate flash memory data sheet (Sharp LHF16506 for EPC16
devices and Micron MT28F400B3 for EPC4 devices) on the Altera web
site at www.altera.com.
External flash interface programming is only allowed when the
configuration controller has relinquished flash access (by tri-stating its
internal interface). If the controller has not relinquished flash access
(during configuration or JTAG-based ISP), you must hold the controller
in reset before initiating external programming. The controller can be
reset by holding the FPGA nCONFIGline at a logic low level. This keeps
the controller in reset by holding the nSTATUS-OEline low, allowing
external flash access.
1
If initial programming of the enhanced configuration device is
done in-system via the external flash interface, the controller
must be kept in reset by driving the FPGA nCONFIGline low to
prevent contention on the flash interface.
2–20
Altera Corporation
August 2005
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
