Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Tables 2–7 through 2–9 describe the enhanced configuration device pins.
These tables include configuration interface pins, external flash interface
pins, JTAG interface pins, and other pins.
Pin Description
Table 2–7. Configuration Interface Pins
Pin Name Pin Type
Description
DATA[7..0] Output
This is the configuration data output bus. DATAchanges on each falling
edge of DCLK. DATAis latched into the FPGA on the rising edge of DCLK.
DCLK
nCS
Output
Input
The DCLKoutput pin from the enhanced configuration device serves as
the FPGA configuration clock. DATAis latched by the FPGA on the rising
edge of DCLK.
The nCSpin is an input to the enhanced configuration device and is
connected to the FPGA’s CONF_DONEsignal for error detection after all
configuration data is transmitted to the FPGA. The FPGA will always drive
nCSand OElow when nCONFIGis asserted. This pin contains a
programmable internal weak pull-up resistor that can be disabled/enabled
in the Quartus II software through the Disable nCS and OE pull-ups on
configuration device option.
nINIT_CONF Open-Drain Output The nINIT_CONFpin can be connected to the nCONFIGpin on the FPGA
to initiate configuration from the enhanced configuration device via a
private JTAG instruction. This pin contains an internal weak pull-up
resistor that is always active. The INIT_CONFpin does not need to be
connected if its functionality is not used. If nINIT_CONFis not used,
nCONFIGmust be pulled to VCC either directly or through a pull-up
resistor.
OE
Open-Drain
Bidirectional
This pin is driven low when POR is not complete. A user-selectable 2-ms
or 100-ms counter holds off the release of OEduring initial power up to
permit voltage levels to stabilize. POR time can be extended by externally
holding OElow. OEis connected to the FPGA nSTATUSsignal. After the
enhanced configuration device controller releases OE, it waits for the
nSTATUS-OEline to go high before starting the FPGA configuration
process. This pin contains a programmable internal weak pull-up resistor
that can be disabled/enabled in the Quartus II software through the
Disable nCS and OE pull-ups on configuration device option.
Altera Corporation
August 2005
2–21
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
