Functional Description
Figure 2–4. FPP Configuration with External Flash Interface
Note (1)
Enhanced Configuration
Device
V
CC
V
CC
PLD or Processor
Stratix Series
or
APEX II Device
WE#C
WE#F
WE#
RP#
RP#C
RP#F
DCLK
DCLK
n
A[20..0]
RY/BY#
CE#
A[20..0] (2)
RY/BY#
CE#
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
DATA[7..0]
OE
nCS
MSEL
nCEO
nINIT_CONF
OE#
OE#
N.C.
DQ[15..0]
DQ[15..0]
nCE
V
CC
V
CC
WP#
BYTE# (3)
VCCW
GND
TM1
PORSEL
(4)
(4)
PGM[2..0]
TMO
EXCLK
(4)
GND
C-A0 (3)
C-A1 (3)
C-A15 (3)
C-A16 (3)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 2–4:
(1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.
(2) Pin A20in EPC16 devices, pins A20and A19in EPC8 devices, and pins A20, A19, and A18in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
(3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15
to F-A15, C-A16to F-A16, and BYTE #to VCC. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP#to F-RP#, C-WE#to F-WE#, TM1to VCC, TM0to
GND, and WP#to VCC
.
(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 2–9.
Dynamic Configuration (Page Mode)
The dynamic configuration or page mode feature allows the enhanced
configuration device to store up to eight different sets of designs for all
the FPGAs in your system. You can then choose which page (set of
configuration files) the enhanced configuration device should use for
FPGA configuration.
2–14
Configuration Handbook, Volume 2
Altera Corporation
August 2005
ALTERA [ ALTERA CORPORATION ]
