Page 30
Timing Information
Table 14. EPC Device Configuration Parameters (Part 2 of 2)
Symbol
tECLK
Parameter
EXCLKinput period
Condition
—
Min
10
4
Typ
—
—
—
—
—
2
Max
Unit
ns
—
—
—
3
tECLKH
tECLKL
tECLKR
tECLKF
EXCLKinput duty cycle high time
EXCLKinput duty cycle low time
EXCLKinput rise time
40% duty cycle
40% duty cycle
100 MHz
100 MHz
2 ms
ns
4
ns
—
—
1
ns
EXCLKinput fall time
3
ns
3
ms
ms
(4)
tPOR
POR time
100 ms
70
100
120
Notes to Table 14:
(1) To calculate tOH, use the following equation: tOH = 0.5 (DCLKperiod) - 2.5 ns.
(2) This parameter is used for CRC error detection by the FPGA.
(3) This parameter is used for CONF
_DONEerror detection by the EPC device.
(4) The FPGA VCCINT ramp time should be less than 1 ms for 2-ms POR and it should be less than 70 ms for 100-ms POR.
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
