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IEEE Std. 1149.1 (JTAG) Boundary-Scan
You can also program the EPC devices using the Quartus II software, the Altera
Programming Unit (APU), and the appropriate configuration device programming
adapter. Table 12 lists which programming adapter to use with each EPC device.
Table 12. Programming Adapters
Device
Package
88-pin UFBGA
Adapter
PLMUEPC-88
EPC16
100-pin PQFP
100-pin PQFP
100-pin PQFP
PLMQEPC-100
PLMQEPC-100
PLMQEPC-100
EPC8
EPC4
IEEE Std. 1149.1 (JTAG) Boundary-Scan
The EPC device provides JTAG BST circuitry that complies with the IEEE Std.
1149.1-1990 specification. JTAG BST can be performed before or after configuration,
but not during configuration.
Figure 6 shows the timing requirements for the JTAG signals.
Figure 6. JTAG Timing Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
tJPZX
tJPCO
tJPXZ
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
Table 13 lists the timing parameters and values for the EPC device.
Table 13. JTAG Timing Parameters and Values (Part 1 of 2)
Symbol Parameter
Min
100
50
Max
—
—
—
—
—
25
Unit
ns
ns
ns
ns
ns
ns
ns
tJCP
TCKclock period
tJCH
TCKclock high time
TCKclock low time
tJCL
50
tJPSU
tJPH
tJPCO
tJPZX
JTAG port setup time
20
JTAG port hold time
45
JTAG port clock output
—
JTAG port high impedance to valid output
—
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Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
