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Power Sequencing
Power Sequencing
Altera requires that you power-up the FPGA's VCCINT supply before the EPC device's
POR expires.
Power up needs to be controlled so that the EPC device’s OEsignal goes high after the
CONF
_
DONEsignal is pulled low. If the EPC device exits POR before the FPGA is
DONEsignal will be high because the pull-up resistor is holding
powered up, the CONF
_
this signal high. When the EPC device exits POR, OEis released and pulled high by a
pull-up resistor. Since the EPC device samples the nCSsignal on the rising edge of OE
,
it detects a high level on CONF_DONEand enters an idle mode. DATAand DCLKoutputs
will not toggle in this state and configuration will not begin. The EPC device will only
exit this mode if it is powered down and then powered up correctly.
1
To ensure the EPC device enters configuration mode properly, you must ensure that
the FPGA completes power-up before the EPC device exits POR.
The pin-selectable POR time feature is useful for ensuring this power-up sequence.
The EPC device has two POR settings—2 ms when PORSELis set to a high level and
100 ms when PORSELis set to a low level. For more margin, the 100-ms setting can be
selected to allow the FPGA to power-up before configuration is attempted.
Alternatively, a power-monitoring circuit or a power-good signal can be used to keep
the FPGA’s nCONFIGpin asserted low until both supplies have stabilized. This ensures
the correct power up sequence for successful configuration.
Programming and Configuration File Support
The Quartus II software provides programming support for the EPC device and
automatically generates the .pof for the EPC4, EPC8, and EPC16 devices. In a
multi-device project, the Quartus II software can combine the .sof for multiple
ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and Stratix series
FPGAs into one programming file for the EPC device.
f For more information about generating programming files, refer to the Altera
Enhanced Configuration Devices.
EPC devices can be programmed in-system through the industry-standard 4-pin
JTAG interface. The ISP feature in the EPC device provides ease in prototyping and
updating FPGA functionality.
After programming an EPC device in-system, FPGA configuration can be initiated by
including the EPC device’s JTAG INIT_CONFinstruction (refer to Table 11).
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
