Package
Page 33
Figure 8 shows the PCB routing for the 88-pin UFBGA package. The Gerber file for
this layout is on the Altera website.
Figure 8. PCB Routing for 88-Pin UFBGA Package (1)
DCLK
DQ7
DQ5
VCC
DQ3
NC
VCC
A20
A16
A11
A8
A15
A10
A14
A9
A13
A12
PGM0
DQ6
GND
DQ14
DQ4
VCC
DQ2
DATA7
DATA5
DATA4
DATA3
DATA2
NC
OE
C-WE#
(2)
DQ15
DQ13
DQ12
VCC
DATA6
nINIT
TCK
TDI
F-WE#
(2)
RY/BY#
(4)
PGM1
VCC
DQ11
CONF
F-RP#
(2)
GND
(5)
TM1
A19
C-RP#
(2)
WP#
TDO
VCCW
DQ10
(3)
TMS
nCS
NC
NC
PGM2
A7
PORSEL
A6
DQ9
A3
DQ8
A2
DQ0
A1
DQ1
DATA1
VCC
NC
A18
A17
VCC
GND
DATA0
GND
EXCLK
A5
A4
A0
CE#
GND
OE#
TM0
GND
NC
Notes to Figure 8:
(1) If the external flash interface feature is not used, then the flash pins should be left unconnected because they are internally connected to the
controller unit. The only pins that need external connections are WP#, WE#, and RP#. If the flash is being used as an external memory source,
then the flash pins should be connected as outlined in the pin descriptions section.
(2) F-RP#and F-WE#are pins on the flash die. C-RP#and C-WE#are pins on the controller die. C-WE#and F-WE#should be connected together
on the PCB. F-RP#and C-RP#should also be connected together on the PCB.
(3) WP#(write protection pin) should be connected to a high level (3.3 V) to be able to program the flash bottom boot block, which is required when
programming the device using the Quartus II software.
(4) RY/BY#is only available in Sharp flash-based EPC devices.
(5) Pin D3is a NCpin for Intel Flash-based EPC16.
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
