Timing Information
Page 29
Table 13. JTAG Timing Parameters and Values (Part 2 of 2)
Symbol
Parameter
Min
—
20
Max
25
Unit
tJPXZ
tJSSU
tJSH
JTAG port valid output to high impedance
Capture register setup time
ns
ns
ns
ns
ns
ns
—
—
25
Capture register hold time
45
—
—
—
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high impedance
25
25
Timing Information
Figure 7 shows the configuration timing waveform when you are using an EPC
device.
Figure 7. Configuration Timing Waveform Using an EPC Device
nINIT_CONF or VCC/nCONFIG
OE/nSTATUS
tPOR
nCS/CONF_DONE
tCH
tDSU
tCL
DCLK
tOEZX
tDH
Byte0 Byte1 Byte2 Byte3
Byten
DATA[7..0]
(2)
tCO
User I/O
User Mode
Tri-State
Tri-State
INIT_DONE
Notes to Figure 7:
(1) The EPC device drives DCLKlow after configuration.
(2) The EPC device drives DATA[]high after configuration.
Table 14 lists the timing parameters when you are using the EPC devices.
Table 14. EPC Device Configuration Parameters (Part 1 of 2)
Symbol Parameter
fDCLK DCLKfrequency
Condition
Min
—
15
6
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Max
66.7
—
Unit
MHz
ns
40% duty cycle
tDCLK
tHC
tLC
DCLKperiod
—
DCLKduty cycle high time
DCLKduty cycle low time
OEto first DCLKdelay
40% duty cycle
—
ns
40% duty cycle
6
—
ns
tCE
—
40
—
ns
tOE
OEto first DATAavailable
DCLKrising edge to DATAchange
OEassert to DCLKdisable delay
OEassert to DATAdisable delay
DCLKrising edge to OE
—
40
(1)
—
ns
tOH
—
—
ns
(2)
tCF
—
277
277
60
—
ns
(2)
(3)
tDF
tRE
tLOE
—
—
ns
—
—
—
ns
OEassert time to assure reset
EXCLKinput frequency
60
—
ns
fECLK
40% duty cycle
—
100
MHz
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
