Programming and Configuration File Support
Page 27
The ISP circuitry in the EPC device is compliant with the IEEE Std. 1532 specification.
The IEEE Std. 1532 is a standard that allows concurrent ISP between devices from
multiple vendors.
(1)
Table 11. JTAG Instructions for EPC Devices
JTAG Instruction
OPCODE
Description
Allows a snapshot of the state of the EPC device pins to be captured and
examined during normal device operation and permits an initial data pattern
output at the device pins.
SAMPLE/
PRELOAD
00 0101 0101
Allows the external circuitry and board-level interconnections to be tested by
forcing a test pattern at the output pins and capturing results at the input pins.
EXTEST
BYPASS
00 0000 0000
11 1111 1111
Places the 1-bit bypass register between the TDIand TDOpins, which allow the
BST data to pass synchronously through a selected device to adjacent devices
during normal device operation.
Selects the device IDCODEregister and places it between TDIand TDO, allowing
the device IDCODEto be serially shifted out to TDO. The device IDCODEfor all
EPC devices is the same and shown below:
IDCODE
00 0101 1001
00 0111 1001
0100A0DDh
Selects the USERCODEregister and places it between TDIand TDO, allowing the
USERCODEto be serially shifted out the TDO. The 32-bit USERCODEis a
programmable user-defined pattern.
USERCODE
This function initiates the FPGA reconfiguration process by pulsing the
nINIT_CONFpin low, which is connected to the FPGA nCONFIGpin. After this
instruction is updated, the nINIT_CONFpin is pulsed low when the JTAG state
machine enters Run-Test/Idlestate. The nINIT_CONFpin is then released
and nCONFIGis pulled high by the resistor after the JTAG state machine goes out
of Run-Test/Idlestate. The FPGA configuration starts after nCONFIGgoes
high. As a result, the FPGA is configured with the new configuration data stored
in flash using ISP. This function can be added to your programming file (.pof,
.jam, and .jbc) in the Quartus II software by enabling the Initiate configuration
after programming option in the Programmer options window (Options menu).
INIT_CONF
00 0110 0001
This optional function can be used to hold the nINIT_CONFpin low during
JTAG-based ISP of the EPC device. This feature is useful when the external flash
interface is controlled by an external FPGA or processor. This function prevents
contention on the flash pins when both the controller and external device try to
access the flash simultaneously. Before the EPC device’s controller can access
the flash memory, the external FPGA/processor needs to tri-state its interface to
flash.This can be ensured by resetting the FPGA using the nINIT_CONF, which
drives the nCONFIGpin and keeps the external FPGA or processor in the “reset”
state. The nINIT_CONFpin is released when the initiate configuration
PENDCFG
00 0110 0101
(INIT_CONF) JTAG instruction is issued.
Note to Table 11:
(1) Instruction register length for the EPC device is 10 and boundary scan length is 174.
f For more information about the EPC device JTAG support, refer to the Configuration
Devices BSDL Files page.
EPC devices can also be programmed by third-party flash programmers or on-board
processors using the external flash interface. Programming files (.pof) can be
converted to a Hexadecimal (Intel-Format) File (.hexout) using the Quartus II Convert
Programming Files utility, for use with the programmers or processors.
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
