Power-On Reset
Page 25
Table 10. JTAG Interface Pins and Other Required Controller Pins (Part 2 of 2)
Pin Name
Pin Type
Description
Optional external clock input pin that can be used to generate the configuration
clock (DCLK).
When an external clock source is not used, connect this pin to a valid logic level
(high or low) to prevent a floating-input buffer. If EXCLKis used, toggling the
EXCLKinput pin after the FPGA enters user mode will not effect the EPC device
operation.
EXCLK
Input
This pin selects a 2-ms or 100-ms POR counter delay during power up. When
PORSELis low, POR time is 100 ms. When PORSELis high, POR time is 2 ms.
PORSEL
Input
This pin must be connected to a valid logic level.
TM0
TM1
Input
Input
For normal operation, this test pin must be connected to GND.
For normal operation, this test pin must be connected to VCC.
Power-On Reset
The POR circuit keeps the system in reset until power-supply voltage levels have
stabilized. The POR time consists of the VCC ramp time and a user-programmable
POR delay counter. When the supply is stable and the POR counter expires, the POR
circuit releases the OEpin. The POR time can be further extended by an external
device by driving the OEpin low.
1
Do not execute JTAG or ISP instructions until POR is complete.
The EPC device supports a programmable POR delay setting. You can set the POR
delay to the default 100-ms setting or reduce the POR delay to 2 ms for systems that
require fast power-up. The PORSELinput pin controls this POR delay—a logic-high
level selects the 2-ms delay, while a logic-low level selects the 100-ms delay.
The EPC device enters reset under the following conditions:
■
■
■
The POR reset starts at initial power-up during VCC ramp-up or if VCC drops
below the minimum operating condition anytime after VCC has stabilized
The FPGA initiates reconfiguration by driving nSTATUSlow, which occurs if the
FPGA detects a CRC error or if the FPGA’s nCONFIGinput pin is asserted
The controller detects a configuration error and asserts OEto begin reconfiguration
of the Altera FPGA (for example, when CONF_DONEstays low after all configuration
data has been transmitted)
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
