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EPC16QI100N 参数 Datasheet PDF下载

EPC16QI100N图片预览
型号: EPC16QI100N
PDF下载: 下载PDF文件 查看货源
内容描述: 该数据表描述了增强型配置( EPC )设备 [This datasheet describes enhanced configuration (EPC) devices]
分类和应用: 存储内存集成电路LTEPC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 36 页 / 621 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Page 22  
Pin Description  
Pin Description  
Table 8 through Table 10 list the EPC device pins. These tables include configuration  
interface pins, external flash interface pins, JTAG interface pins, and other pins.  
Table 8. Configuration Interface Pins  
Pin Name  
Pin Type  
Output  
Description  
Configuration data output bus. DATAchanges on each falling edge of DCLK. DATA  
DATA[7..0]  
is latched into the FPGA on the rising edge of DCLK  
The DCLKoutput pin from the EPC device serves as the FPGA configuration clock.  
DATAis latched by the FPGA on the rising edge of DCLK  
The nCS pin is an input to the EPC device and is connected to the FPGA’s  
DONEsignal for error detection after all configuration data is transmitted to  
.
DCLK  
Output  
.
CONF  
_
the FPGA. The FPGA will always drive nCSand OElow when nCONFIGis asserted.  
This pin contains a programmable internal weak pull-up resistor of 6 Kthat can  
be disabled or enabled in the Quartus II software through the Disable nCS and  
OE pull-ups on configuration device option.  
nCS  
Input  
The nINIT_CONFpin can be connected to the nCONFIGpin on the FPGA to  
initiate configuration from the EPC device using a private JTAG instruction. This  
pin contains an internal weak pull-up resistor of 6K that is always active. The  
nINIT_CONF  
Open-Drain Output  
INIT  
_CONFpin does not need to be connected if its functionality is not used. If  
n
INIT  
_
CONFis not used, nCONFIGmust be pulled to VCC either directly or  
through a pull-up resistor.  
This pin is driven low when POR is not complete. A user-selectable 2-ms or  
100-ms counter holds off the release of OEduring initial power up to permit  
voltage levels to stabilize. POR time can be extended by externally holding OElow.  
OEis connected to the FPGA nSTATUSsignal. After the EPC device controller  
Open-Drain  
Bidirectional  
OE  
releases OE, it waits for the nSTATUS-OEline to go high before starting the FPGA  
configuration process. This pin contains a programmable internal weak pull-up  
resistor of 6 Kthat can be disabled or enabled in the Quartus II software  
through the Disable nCS and OE pull-ups on configuration device option.  
Enhanced Configuration (EPC) Devices Datasheet  
January 2012 Altera Corporation  
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