Functional Description
Page 21
Programming using External Flash Interface
This method allows parallel programming of the flash memory using the 16-bit data
bus. An external processor or FPGA acts as the flash controller and has access to
programming data using a communication link such as UART, Ethernet, and PCI. In
addition to the program, erase, and verify operations, the external flash interface
supports block or sector protection instructions.
External flash interface programming is only allowed when the configuration
controller has relinquished flash access by tri-stating its internal interface. If the
controller has not relinquished flash access during configuration or JTAG-based ISP,
you must hold the controller in reset before initiating external programming. The
controller can be reset by holding the FPGA nCONFIGline at a logic low level. This
keeps the controller in reset by holding the nSTATUS-OEline low, allowing external
flash access.
1
If initial programming of the EPC device is done in-system using the external flash
interface, the controller must be kept in reset by driving the FPGA nCONFIGline low to
prevent contention on the flash interface.
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
