Page 12
Functional Description
Figure 3 shows the schematic for configuring multiple FPGAs concurrently in the PS
mode using an EPC device.
Figure 3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
EPC Device
V
CC
(1)
V
CC
(1)
WE#C
WE#F
RP#F
(3)
(3)
FPGA0
RP#C
DCLK
DATA0
DCLK
DATA0
N.C.
N.C.
N.C.
A[20..0]
RY/BY#
CE#
n
nSTATUS
CONF_DONE
nCONFIG
(6)
MSEL
nCEO
DATA1
N.C.
OE#
nCE
(3)
OE
N.C.
DQ[15..0]
N.C.
n
(3)
nCS
nINIT_CONF (2)
GND
FPGA1
DCLK
DATA 7
DATA0
nSTATUS
CONF_DONE
nCONFIG
(6)
MSEL
nCEO
(1)
V
(7)
CC
V
CC
VCCW
nCE
WP#
BYTE# (5)
N.C.
TM1
GND
(4)
PORSEL
(4)
PGM[2..0]
EXCLK
(4)
FPGA7
DCLK
n
DATA0
nSTATUS
CONF_DONE
TMO
(6)
MSEL
nCEO
nCONFIG
GND
nCE
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
N.C.
GND
Notes to Figure 3:
(1) Connect VCC to the same supply voltage as the EPC device.
(2) The nINIT CONFpin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT CONFor nCONFIGsignal. The nINIT CONFpin does not need to be connected if its functionality is not
used. If nINIT CONFis not used, nCONFIGmust be pulled to VCC either directly or through a resistor.
_
_
_
_
(3) The EPC devices’ OEandnCSpins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0
and BYTE#to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP#to F-
RP# C-WE#to F-WE# TM1to VCC TM0to GND, and WP#to VCC
, PGM[], and EXCLKpin connections, refer to Table 10 on page 24.
,
C-A1to F-A1, C-A15to F-A15, C-A16to F-A16,
,
,
,
.
(6) Connect the FPGA MSEL[]input pins to select the PS configuration mode. For more information, refer to the configuration chapter in the
appropriate device handbook.
(7) To protect Intel Flash based EPC devices content, isolate the VCCW supply from VCC. For more information, refer to“Intel Flash-Based EPC Device
Protection” on page 16.
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
